1. Field of the Invention
The present invention relates generally to single transistor random access memory (1T-RAM) cell structures. More particularly, the present invention relates-to single transistor random access memory cell structures with enhanced performance.
2. Description of the Related Art
Common in the semiconductor product fabrication art is the fabrication of single transistor random access memory cell structures. A single transistor random access memory cell structure typically comprise a transistor as a switching device connected with a capacitor as a digital data storage device. Access to digital data stored within the capacitor is effected by switching operation of the transistor.
While single transistor random access memory cell structures are quite common in the semiconductor product fabrication art and often essential in the semiconductor product fabrication art, single transistor random access memory cell structures are nonetheless not entirely without problems.
In that regard, it is often difficult to fabricate single transistor random access memory cell structures with enhanced performance with respect to both transistors and capacitors formed therein.
It is towards the foregoing object that the present invention is directed.
Various semiconductor products having desirable properties, and methods for fabrication thereof, have been disclosed within the semiconductor product fabrication art.
Included but not limiting among the semiconductor products and methods for fabrication thereof are semiconductor products and methods for fabrication thereof disclosed within: (1) Barsan et al., in U.S. Pat. No. 5,672,521 (a method for fabricating a semiconductor substrate such as to provide multiple gate oxide layers of multiple thicknesses formed thereupon); (2) Gardner et al., in U.S. Pat. No. 5,918,133 (a method for fabricating a semiconductor device having a gate dielectric layer having two different thickness regions); and (3) Hasegawa, in U.S. Pat. No. 6,091,109 (another method for fabricating a semiconductor substrate such as to provide multiple gate oxide layers of multiple thicknesses formed thereupon).
The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable are additional single transistor random access memory cell structures with enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a single transistor random access memory cell structure.
A second object of the invention is to provide a single transistor random access memory cell structure in accord with the first object of the invention, wherein the single transistor random access memory cell structure has enhanced performance.
In accord with the objects of the invention, the invention provides a single transistor random access memory cell structure and a method for fabricating the single transistor random access memory cell structure.
In accord with the invention, the single transistor random access memory cell structure comprises a semiconductor substrate having a minimum of one active region defined therein. The single transistor random access memory cell structure also comprises a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within the minimum of one active region. Within the single transistor random access memory cell structure: (1) a single fluorinated silicon oxide layer of a single thickness serves as both a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the metal oxide semiconductor capacitor device; and (2) a channel region within the field effect transistor device has a different threshold voltage adjusting dopant concentration in comparison with a semiconductor plate region within the metal oxide semiconductor capacitor device.
The single transistor random access memory cell structure of the present invention contemplates a method for fabricating the single transistor random access memory cell structure of the present invention.
The present invention provides a single transistor random access memory cell structure, wherein the single transistor random access memory cell structure has enhanced performance.
The present invention realizes the foregoing object within the context of a single transistor random access memory cell structure comprising a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within an active region of a semiconductor substrate, by employing: (1) a single fluorinated silicon oxide layer of a single thickness as both a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the metal oxide semiconductor capacitor device; and (2) a channel region within the field effect transistor device with a different threshold voltage adjusting dopant concentration in comparison with a semiconductor plate region within the metal oxide semiconductor capacitor device.